This invention concerns the creation of dielectric layers or doped polymeric layers for electronic applications, particularly multilevel metallized circuits.
The prior art has formed insulating layers on silicon semiconductor substrates by chemical vapor deposition techniques. In such procedures a volatile silicon compound is decomposed and oxidized in the gas phase and then deposited on the substrate.
Unfortunately, this traditional chemical vapor deposition technique will result in increased fabrication problems for future integrated circuits with perhaps 3, 5, 10, or more interconnection layers. The inability of vapor systems to planarize the surface they are insulating will be an increasing problem, particularly to photolithographic steps in the fabrication process. Moreover, the vapor deposited doped silicon oxide interlayers are brittle and must be protected from water.
Ladder-type organosiloxanes have been described as useful for forming interlayer dielectric films (U.S. Pat. No. 4,600,685). These are apparently formed by hydrolytic polycondensation of organotrihalosilanes such as phenyltrichlorosilane. Doping of interlayer dielectric compositions is not described therein.
Spin-on deposition has been proposed as an application method by Chang et al. in a paper presented to The Electrochemical Society in mid-May of 1985 in Toronto, Canada.
U.S. Pat. No. 4,663,414 to W. E. Estes et al. describes doped spin-on polymers of a silsesquioxane-based copolymer type.
A need exists for improved polymers suitable for use as interlayer dielectrics.